Data bus system, its encoder/decoder and encoding/decoding method
US8181101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2009 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Feb 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, the mapping is such that the Hamming distance between any possible value of the virtual bit-group and a reference virtual bit-group which cannot be converted into under the mapping is a fixed value, and not greater than the number of error-correction bits of the error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.