System and method for providing compliant mapping between chip bond locations and package bond locations for an integrated circuit
US8181125B2 · kind B2 · utility
5Cited by
12References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2002 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Aug 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for providing compliant mapping between chip bond locations of an IC and corresponding package bond locations is disclosed. Package design information including package bond location information relating to the IC package and IC mask data including chip bond location information relating to the IC chip are integrated such that an internal physical design verification tool is operable to verify compliance between package bond locations and chip bond locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.