Patterning embedded control lines for vertically stacked semiconductor elements
US8183126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2009 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Feb 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
Abstract
Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.