Semiconductor memory device
US8183552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2009 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Aug 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/00
Abstract
A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.