Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same
US8183665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2008 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | May 30, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/943
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-density memory array. A plurality of word lines and a plurality of bit lines are arranged to access a plurality of memory cells. Each memory cell includes a first conductive terminal and an article in physical and electrical contact with the first conductive terminal, the article comprising a plurality of nanoscopic particles. A second conductive terminal is in physical and electrical contact with the article. Select circuitry is arranged in electrical communication with a bit line of the plurality of bit lines and one of the first and second conductive terminals. The article has a physical dimension that defines a spacing between the first and second conductive terminals such that the nanotube article is interposed between the first and second conducive terminals. A logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.