Patent · US Active

Memory circuit having memory chips parallel connected to ports and corresponding production method

US8183676B2 · kind B2 · utility

0Cited by

4References

31Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Simon Muff · Mering, DE
Hermann Ruckerbauer · Radolfzell, DE

Key dates

Filing date	Apr 18, 2007
Grant date	May 22, 2012
Priority date	—
Expiry date	Jan 19, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15311
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory circuit includes multiple memory chips configured to store data and disposed in at least one stack. The memory circuit includes multiple ports configured to receive and transmit control signals and data to and from the memory chips and to supply energy to the memory circuit. The memory circuit includes a housing accommodating the multiple memory chips and the multiple ports.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.