Structure of stacking scatterometry based overlay marks for marks footprint reduction
US8183701B2 · kind B2 · utility
6Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2009 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Apr 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F9/7084
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.