Integrated circuit reconfiguration techniques
US8183883B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Apr 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory configuration circuit is provided. The memory configuration circuit may be integrated into a programmable logic device (PLD) and as such, may be used to configure and reconfigure specific elements in the PLD. The memory configuration circuit includes a comparator circuit and a counter. The comparator circuit is coupled to receive two data words from two different memory configuration sources. The comparator circuit compares the two data words received before writing one of the data words to a configuration memory. One of the data words may be written to the configuration memory if the two data words compared are not equal. The counter increments the address of the memory configuration sources so that a next data word can be processed after the current data word is processed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.