Circuitry and method for reducing second and third-order nonlinearities
US8183918B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2008 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | May 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/21178
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic circuit comprises at least two transistors coupled in parallel, wherein the second transistor channel length is configured such that the threshold voltage of the second transistor is at a peak on a threshold voltage versus channel lengths curve arising from reverse short channel effects for a given semiconductor process. The first transistor is biased with a first gate-source voltage and a first drain-source voltage. The second transistor is biased with a second gate-source voltage and a second drain-source voltage. The first and second gate-source voltages are offset from each other by a gate-source voltage offset. The first and second drain-source voltages are offset from each other by a drain-source voltage offset. These bias conditions result in the transistors operating in different regions so that the second and third-order nonlinearities of the transistors substantially cancel each other out simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.