Offset cancellation for continuous-time circuits
US8183921B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Nov 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45374
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.