Mobile industry processor interface
US8184026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Oct 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An optimized Mobile Industry Processor Interface (MIPI) includes a transmitter physical (PHY) layer configured to convert input data into serial data and transmit the serial data in synchronization with a high-speed clock, a receiver PHY layer configured to convert the serial data into 8-bit parallel data in synchronization with the clock received from the transmitter, a bit merge block configured to merge the parallel data received from the receiver PHY layer so as to form 32-bit data using multiple lanes and to transmit the 32-bit data to a receiver protocol layer, the receiver protocol layer being configured to decode and recognize the data received from the bit merge block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.