DRAM having stacked capacitors of different capacitances
US8184471B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2009 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Sep 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM device having a plurality of memory blocks, including edge-located memory blocks and adjacent central memory blocks. An edge-located memory block shares a sense amplifier with an adjacent central memory block. The memory cells in the edge-located memory block include data storage capacitors having a greater capacitance value than data storage capacitors in the memory cells in the adjacent central memory block. The data storage capacitors in edge-located memory cells may have greater surface area than data storage capacitors in the central memory cells. The data storage capacitors in edge-located memory cells may be formed by connecting in parallel two data storage capacitors of the shape and size of data storage capacitors used in each of the memory cells of the adjacent central memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.