PLD architecture optimized for 10G Ethernet physical layer solution
US8184651B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2008 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Dec 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/352
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10 GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.