Digital phase lock loop with multi-phase master clock
US8184762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2008 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Mar 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase lock loop circuit provides an output with reduced jitter. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.