Three-term input floating-point adder-subtractor
US8185570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2007 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Jan 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49963
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, which reduces the mantissas from three to two terms, which carries out addition on the mantissas of the two terms, a normalization circuit which makes left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which outputs a final exponent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.