Processor instruction set for controlling threads to respond to events
US8185722B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2007 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Jul 13, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a processor comprising an execution unit and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective status for each thread. The execution unit is configured to execute thread scheduling instructions which manage said statuses, the thread scheduling instructions including at least: a thread event enable instruction which sets a status to event-enabled to allow a thread to accept events, a wait instruction which sets the status to suspended pending at least one event upon which continued execution of the thread depends, and a thread event disable instruction which sets the status to event-disabled to stop the thread from accepting events. The continued execution comprises retrieval of a continuation point vector for the thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.