Test device and method for hierarchical test architecture
US8185782B2 · kind B2 · utility
3Cited by
10References
41Claims
0Family size
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Key dates
| Filing date | Nov 26, 2008 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Nov 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318586
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test device for a hierarchical test architecture is disclosed. The architecture includes cores for plural test layers, a top-level data register, and a top-level test controller. Cores for each test layer are hierarchical test circuits. The top-level test controller retrieves plural control signals, controls the top-level data register based on first type control signals in the control signals, and controls each core based on second type control signals in the control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.