Single event upset error detection within an integrated circuit
US8185812B2 · kind B2 · utility
12Cited by
100References
31Claims
0Family size
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Key dates
| Filing date | Dec 11, 2006 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Oct 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/183
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.