Architectural level power-aware optimization and risk mitigation
US8185862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Nov 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.