Mask level reduction for MOSFET
US8187929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2009 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Dec 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
A method of fabricating a thin film transistor for an active matrix display using reduced masking operations includes patterning a gate on a substrate. A gate dielectric is formed over the gate and a semiconducting metal oxide is deposited on the gate dielectric. A channel protection layer is patterned on the semiconducting metal oxide overlying the gate to define a channel area and to expose the remaining semiconducting metal oxide. A source/drain metal layer is deposited on the structure and etched through to the channel protection layer above the gate to separate the source/drain metal layer into source and drain terminals and the source/drain metal layer and the semiconducting metal oxide are etched through at the periphery to isolate the transistor. A nonconductive spacer is patterned on the transistor and portions of the surrounding source/drain metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.