Integrated circuit structure with electrical strap and its method of forming
US8188550B2 · kind B2 · utility
5Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2008 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Dec 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.