Clock system and method for compensating timing information of clock system
US8188782B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2010 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Feb 2, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock system includes a clock signal generating circuit and a controlling circuit. The clock signal generating circuit is used for generating a primary clock signal and a reference clock signal both derived from an oscillating signal of the clock signal generating circuit. The controlling circuit is coupled to the clock signal generating circuit and used for receiving the primary clock signal under a normal mode and compensating timing information generated from the primary clock signal according to the reference clock signal when the clock system exits a power saving mode. The primary clock signal is de-activated when the clock system enters the power saving mode and is activated when the clock system exits the power saving mode. The clock system can keep a continue clock for system to use when the primary clock signal is gated or power saving mode is entered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.