Systems and methods for saturation detection and corection in a power control loop
US8188793B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2008 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Jul 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are described for detecting and correcting saturation in a power amplification circuit. An exemplary circuit comprises a power amplifier that provides an amplified output signal based upon an input signal and a gain control signal; a power detector that provides a detector signal indicative of the amplified signal magnitude; an error amplifier that generates the gain control signal based upon a setpoint signal and the detector signal; and a saturation detector that provides a saturation detection signal indicating whether gain control signal exceeds a reference signal. In another embodiment the circuit comprises an offset generator that provides a correction to the setpoint signal in response to the saturation detection signal indicating that the gain control signal exceeds the reference signal. In still another embodiment the circuit includes an offset cutoff circuit that freezes the correction to the setpoint signal in response to the correction exceeding a threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.