Non-volatile memory counter
US8189732B1 · kind B1 · utility
7Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2010 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Nov 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A counter is efficiently implemented in non-volatile memory by using two binary counters and selectively using one or the other as a current counter. Writes to the binary counters are minimized by using two linear counters and using the state of the binary counters to determine which binary counter contains the current count. Write operations can be performed to the “not current” binary counter with the final write operation being to the linear counters. The linear counter write operations can be in program-only mode so that a power failure will not result in a loss of counts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.