Various methods and apparatus for a memory scheduler with an arbiter
US8190804B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2009 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Sep 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1615
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.