Memory device having staggered memory operations
US8190808B2 · kind B2 · utility
15Cited by
112References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2004 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Sep 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.