Handling of errors in a data processing apparatus having a cache storage and a replicated address storage
US8190951B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 2009 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Sep 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus includes processing circuitry, a cache storage, and a replicated address storage having a plurality of entries. On detecting a cache record error, a record of a cache location avoid storage is allocated to store a cache record identifier for the accessed cache record. On detection of an entry error, use of the address indication currently stored in that accessed entry of the replicated address storage is prevented, and a command is issued to the cache location avoid storage. In response, a record of the cache location avoid storage is allocated to store the cache record identifier for the cache record of the cache storage associated with the accessed entry of the replicated address storage. Any cache record whose cache record identifier is stored in the cache location avoid storage is logically excluded from the plurality of cache records.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.