Parity check matrix storing method, block LDPC coding method, and apparatus using parity check matrix storing method
US8190967B2 · kind B2 · utility
85Cited by
2References
16Claims
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Key dates
| Filing date | Sep 26, 2007 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Mar 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a low density parity check (LDPC) encoding method and an apparatus thereof. In the LDPC encoding method, a matrix multiplication corresponding to ET−1 and T−1 is eliminated according to a structural characteristic in an encoding process. Accordingly, shift weights that are not −1 among shift weights corresponding to partial blocks A, B, and C of a parity check matrix are used to perform an encoding operation, and a cyclic shift operation of an information unit block is performed in parallel so that a first parity block and a second parity block may be simultaneously generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.