Single event transient mitigation and measurement in integrated circuits
US8191021B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 2009 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | May 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. Provision is made for applying the method to logic designs implemented in programmable logic integrated circuit devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.