Nanoelectronic device
US8193524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2009 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Dec 4, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/762
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.