Monolithic semiconductor switches and method for manufacturing

US8193559B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Oliver Haeberlen · Villach, AT
• Walter Rieger · Arnoldstein, AT
• Martin Vielemeyer · Villach, AT
• Lutz Goergens · Villach, AT
• Martin Poelzl · Ossiach, AT
• Milko Paolucci · Villach, AT
• Johannes Schoiswohl · San Jose, US
• Joachim Krumrey · Eisenlohrsweg, AT

Key dates

• Filing date: Apr 7, 2011
• Grant date: Jun 5, 2012
• Expiry date: Apr 7, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0195
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.