Patent · US Active

Semiconductor packaging process using through silicon vias

US8193615B2 · kind B2 · utility

40Cited by

30References

32Claims

0Family size

Assignee

Digitaloptics Corporation Europe Limited · IE

Inventors

Belgacem Haba · Cupertino, US
Giles Humpston · San Jose, US
Moti Margalit · Zichron Ya'akov, IL

Key dates

Filing date	Jul 31, 2008
Grant date	Jun 5, 2012
Priority date	—
Expiry date	Jul 31, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/12044
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A microelectronic unit 400 can include a semiconductor element 401 having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts 403 at the front surface and a rear surface remote from the front surface. The semiconductor element 401 can have through holes 410 extending from the rear surface through the semiconductor element 401 and through the contacts 403. A dielectric layer 411 can line the through holes 410. A conductive layer 412 may overlie the dielectric layer 411 within the through holes 410. The conductive layer 412 can conductively interconnect the contacts 403 with unit contacts.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.