Data width scaler circuitry
US8193953B1 · kind B1 · utility
2Cited by
5References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2010 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Oct 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/28
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuitry for scaling data from a first width (e.g., number of simultaneously presented parallel data signals) to a second width can preferably operate for any of a wide range of different ratios between the first and second widths (including ratios that are non-integer or even non-rational) without the need for more than one clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.