Interleaved memory program and verify method, device and system
US8194454B2 · kind B2 · utility
2Cited by
17References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 9, 2011 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Aug 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.