Semiconductor memory devices having bit lines
US8194486B2 · kind B2 · utility
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5References
19Claims
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Key dates
| Filing date | Nov 25, 2009 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Feb 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.