Packet processing in a parallel processing environment
US8194690B1 · kind B1 · utility
38Cited by
16References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2007 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Feb 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/52
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Packets are processed in a system that comprises a plurality of interconnected processor cores. The system receives packets into one or more queues. The system associates at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate. The system maps a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and based on at least one rate associated with a node not in the set. The packets are processed in one or more processor cores including the mapped processor core according to the hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.