Signal amplitude distortion within an integrated circuit
US8194721B2 · kind B2 · utility
1Cited by
29References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2008 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Aug 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/243
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated circuit 2 includes a serial data transmitter 12 and a serial data receiver 14. A signal amplitude distorting circuit 30 is provided to introduce distortion in the amplitude of a serial data signal generated by the serial data transmitter 12 and looped back to the serial data receiver 14 so as to stress test the serial data receiver 14.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.