Method and apparatus for implementing processor instructions for accelerating public-key cryptography
US8194855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2003 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Jun 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5318
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to executing a single arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is added implicitly to generate a result that represents the first number multiplied by the second number summed with the partial result from a previously executed single arithmetic instruction. The high order portion of the generated result is saved in an extended carry register as a next partial result for use with execution of a subsequent single arithmetic instruction. Execution of a single arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.