Systems, devices, and methods for interconnected processor topology
US8195596B2 · kind B2 · utility
200Cited by
7References
34Claims
0Family size
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Key dates
| Filing date | Jan 11, 2008 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Apr 7, 2031 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An analog processor, for example a quantum processor may include a plurality of elongated qubits that are disposed with respect to one another such that each qubit may selectively be directly coupled to each of the other qubits via a single coupling device. Such may provide a fully interconnected topology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.