Resource sharing to reduce implementation costs in a multicore processor
US8195883B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2010 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Dec 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0813
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.