Structure for silent invalid state transition handling in an SMP environment
US8195892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2008 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Jan 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design can be provided. The design structure includes a symmetric multiprocessing (SMP) system. The system includes a plurality of nodes. Each of the nodes includes a node controller and a plurality of processors cross-coupled to one another. The system also includes at least one cache directory coupled to each node controller, and, invalid state transition logic coupled to each node controller. The invalid state transition logic includes program code enabled to identify an invalid state transition for a cache line in a local node, to evict a corresponding cache directory entry for the cache line, and to forward an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.