System for dynamically allocating processing time to multiple threads
US8195922B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2005 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Dec 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipeline processor architecture, processor, and methods are provided. In one implementation, a processor is provided that includes an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, a decoder responsive to the instruction fetch unit, issue logic responsive to the decoder, and a register file including a plurality of banks corresponding to the plurality of processor threads. Each bank is operable to store data associated with a corresponding processor thread. The processor can include a set of registers corresponding to each of a plurality of processor threads. Each register within a set is located either before or after a pipeline stage of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.