Interactive design optimization techniques and interface
US8196085B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2010 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Oct 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for analyzing and optimizing a design on an integrated circuit (IC) are provided. The techniques include an interface that aids interactive optimization. A visual indicator is generated based on the power usage value of each of the logic blocks in the design. The visual indicator can be overlaid on top of a floorplan layout of the IC to highlight the parts of the design that may be further optimized. The visual indicator can be updated in real time to highlight the optimizations that have been achieved by the changes made to the design. The real time update of the visual indicator may allow multiple changes to be made to the design before the design is recompiled with a design program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.