Regular pattern arrays for memory and logic on a semiconductor substrate

US8198655B1 · kind B1 · utility

Assignee

• CARNEGIE MELLON UNIVERSITY · US

Inventors

• Lawrence Pileggi · Pittsburgh, US
• Daniel Henry Morris · Mountain View, US

Key dates

• Filing date: Apr 27, 2009
• Grant date: Jun 12, 2012
• Expiry date: Mar 1, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/90

Abstract

An integrated circuit comprising both memory and logic wherein at least one layer of the integrated circuit is fabricated using a common grating pattern for both memory and logic is described. In one embodiment, the integrated circuit comprises a substrate, an active layer, and a gate material layer such as a polysilicon layer, and the active layer, the gate material layer, or both the active layer and the gate material layer are formed using a common grating pattern for both memory and logic. By using a common grating pattern for both memory and logic, a corresponding layer of the integrated circuit can be reliably and affordably manufactured using sub-wavelength lithography.