Thin film transistor array panel and method for manufacturing the same
US8198657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2010 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Dec 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
Abstract
A thin film transistor array panel includes an insulating substrate. A gate line is formed on the insulating substrate and has a gate electrode. A gate insulating layer is formed on the gate line. A semiconductor layer is formed on the gate insulating layer and overlaps the gate electrode. Diffusion barriers are formed on the semiconductor layer and contain nitrogen. A data line crosses the gate line and has a source electrode partially contacting the diffusion barriers and a drain electrode partially contacting the diffusion barriers and facing the source electrode. The drain electrode is on the gate electrode. A pixel electrode is electrically connected to the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.