Current segmentation circuit for optimizing output waveform for high speed data transmission interface
US8198917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2009 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Aug 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention provides a current segmentation circuit for optimizing output waveform from high speed data transmission interface, which comprises a four current sources controlled by four switches to segment current so as to control the rising and falling time of the high speed transmission data, and to match the delay of the current control signal and the delay of the data, wherein the four current sources are I1, I2, I3 and I4, and the current control switches are K1, K2, K3 and K4, wherein I1+I2=I3+I4, wherein the switches K1 and K3 control the current I1/I3 to flow into DP/DM line, and the switches K2 and K4 control the current I2/I4 to flow into DP/DM line. The present invention can depress overshoot and eliminate turning point in the waveform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.