Digital power on reset
US8198925B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2009 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Feb 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus is implemented with a digital electronic component that produces a clock signal. The apparatus also includes a first counter that outputs a first count signal based on the clock signal and a second counter that outputs a second count signal based on the clock signal. The apparatus also includes a power on reset logic that selectively provides a power on reset signal based on the first count signal and the second count signal. The power on reset logic can also selectively disable the apparatus upon providing the power on reset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.