System on chip including an image processing memory with multiple access
US8199157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2008 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Sep 28, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system on chip (Soc) includes a system bus, a plurality of sub-systems, an image processing logic block, an image memory interface and an image processing memory block. The sub-systems are respectively connected to the system bus. The image processing logic block is connected to the system bus. The image processing logic block performs an image processing. The image processing logic block is included in a first power domain. The image memory interface is connected to the system bus and the image processing logic block. The image processing memory block is connected to the image memory interface. The image processing memory block is used for the image processing. The image memory interface and the image processing memory block are included in a second power domain different from the first power domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.