Method and apparatus for controlling cache memory
US8200900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2009 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Feb 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for controlling a cache memory that stores therein data transferred from a main storing unit includes a computing processing unit that executes a computing process using data, a connecting unit that connects an input portion and an output portion of the cache memory, a control unit that causes data in the main storing unit to be transferred to the output portion of the cache memory through the connecting unit when the data in the main storing unit is input from the input portion of the cache memory into the cache memory, and a transferring unit that transfers data transferred by the control unit to the output portion of the cache memory, to the computing processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.