Patent · US Active

Memory management unit in a microprocessor system

US8200939B2 · kind B2 · utility

0Cited by

9References

24Claims

0Family size

Assignee

ARM Norway AS · NO

Inventors

Edvard Sørgård · Trondheim, NO
Jørn Nystad · Trondheim, NO
Androas Due Engh-Halstvedt · Trondheim, NO

Key dates

Filing date	Jan 31, 2008
Grant date	Jun 12, 2012
Priority date	—
Expiry date	Mar 10, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/1027
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory management arrangement includes a memory management unit, a cache memory and a queue arrangement. The queue is a first-in, first-out (FIFO) buffer which can queue failed memory access requests and return them as inputs to the memory management unit via the bus 5 for retrying through the memory management unit at a later time. If a memory access request sent to the memory management unit experiences a cache “miss”, instead of blocking memory access requests until the required address data has been loaded into the cache, the memory management unit operates to place the failed memory access request in the replay queue, and allows subsequent memory access requests to continue. The failed memory access requests in the queue are then continuously circulated through the memory management unit from the queue alternately with new memory access requests from other access initiators.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.